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SN65LV1023A/SN65LV1224B 10 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS621A - SEPTEMBER 2004 - REVISED JANUARY 2005
D 100-Mbps to 660-Mbps Serial LVDS Data D D D
Payload Bandwidth at 10-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224 Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz Synchronization Mode for Faster Lock
SN65LV1023A Serializer
D D D D D D
Lock Indicator No External Components Required for PLL Low-Cost 28-Pin SSOP Package Industrial Temperature Qualified, TA = -40C to 85C Programmable Edge Trigger on Clock Flow-Through Pinout for Easy PCB Layout
SN65LV1224B Deserializer
SYNC1 SYNC2 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 TCLK_R/F TCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
DVCC DVCC AVCC AGND PWRDN AGND D O+ D O- AGND DEN AGND AVCC DGND DGND
AGND RCLK_R/F REFCLK AVCC RI+ RI- PWRDN REN RCLK LOCK AVCC AGND AGND DGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 DVCC DGND DVCC DGND ROUT5 ROUT6 ROUT7 ROUT8 ROUT9
description
The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters. The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock. The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of -40C to 85C.
ORDERING INFORMATION DEVICE Serializer Deserializer PART NUMBER SN65LV1023ADB SN65LV1224BDB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2004 - 2005, Texas Instruments Incorporated
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SN65LV1023A/SN65LV1224B 10 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS621A - SEPTEMBER 2004 - REVISED JANUARY 2005
block diagrams
SN65LV1023A SN65LV1224B
LVDS Parallel-to-Serial Serial-to-Parallel 10 Input Latch DIN A+ A- Y+ Y- 10 Output Latch DOUT
TCLK_R/F
TCLK (10 MHz to 66 MHz)
PLL
Timing / Control
DEN
PLL
Timing / Control
REFCLK REN LOCK RCLK_R/F RCLK (10 MHz to 66 MHz)
SYNC1 SYNC2
Clock Recovery
functional description
The SN65LV1023A and SN65LV1224B are a 10-bit serializer/deserializer chipset designed to transmit data over differential backplanes or unshielded twisted pair (UTP) at clock speeds from 10 MHz to 66 MHz. The chipset has five states of operation: initialization mode, synchronization mode, data transmission mode, power-down mode, and high-impedance mode. The following sections describe each state of operation. initialization mode Initialization of both devices must occur before data transmission can commence. Initialization refers to synchronization of the serializer and deserializer PLLs to local clocks. When VCC is applied to the serializer and/or deserializer, the respective outputs enter the high-impedance state, while on-chip power-on circuitry disables internal circuitry. When VCC reaches 2.45 V, the PLL in each device begins locking to a local clock. For the serializer, the local clock is the transmit clock (TCLK) provided by an external source. For the deserializer, a local clock must be applied to the REFCLK pin. The serializer outputs remain in the high-impedance state, while the PLL locks to the TCLK.
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functional description (continued)
synchronization mode The deserializer PLL must synchronize to the serializer in order to receive valid data. Synchronization can be accomplished in one of two ways:
D Rapid Synchronization: The serializer has the capability to send specific SYNC patterns consisting of six
ones and six zeros switching at the input clock rate. The transmission of SYNC patterns enables the deserializer to lock to the serializer signal within a deterministic time frame. This transmission of SYNC patterns is selected via the SYNC1 and SYNC2 inputs on the serializer. Upon receiving valid SYNC1 or SYNC2 pulse (wider than 6 clock cycles), 1026 cycles of SYNC pattern are sent. When the deserializer detects edge transitions at the LVDS input, it attempts to lock to the embedded clock information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC patterns present on the serial input. When the deserializer locks to the LVDS data, the LOCK output goes low. When LOCK is low, the deserializer outputs represent incoming LVDS data. One approach is to tie the deserializer LOCK output directly to SYNC1 or SYNC2.
D Random-Lock Synchronization: The deserializer can attain lock to a data stream without requiring the
serializer to send special SYNC patterns. This allows the SN65LV1224B to operate in open-loop applications. Equally important is the deserializer's ability to support hot insertion into a running backplane. In the open-loop or hot-insertion case, it is assumed the data stream is essentially random. Therefore, because lock time varies due to data stream characteristics, the exact lock time cannot be predicted. The primary constraint on the random lock time is the initial phase relation between the incoming data and the REFCLK when the deserializer powers up. The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer could enter false lock--falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive multitransition (RMT); see Figure 1 for RMT examples. This occurs when more than one low-high transition takes place per clock cycle over multiple cycles. In the worst case, the deserializer could become locked to the data pattern rather than the clock. Circuitry within the deserializer can detect that the possibility of false lock exists. Upon detection, the circuitry prevents the LOCK output from becoming active until the potential false lock pattern changes. Notice that the RMT pattern only affects the deserializer lock time, and once the deserializer is in lock, the RMT pattern does not affect the deserializer state as long as the same data boundary happens each cycle. The deserializer does not go into lock until it finds a unique four consecutive cycles of data boundary (stop/start bits) at the same position. The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive cycles. Then the deserializer goes out of lock and hunts for the new data boundary (stop/start bits). In the event of loss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter a high-impedance state. The user's system should monitor the LOCK pin in order to detect a loss of synchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable if reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as previously noted.
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SN65LV1023A/SN65LV1224B 10 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
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synchronization mode (continued)
DIN0 Held Low and DIN1 Held High Stop Bit Start Bit Stop Bit Start Bit
DIN0
DIN1
DIN4 Held Low and DIN5 Held High Stop Bit Start Bit Stop Bit Start Bit
DIN4
DIN5
DIN8 Held Low and DIN9 Held High Stop Bit Start Bit Stop Bit Start Bit
DIN8
DIN9
Figure 1. RMT Pattern Examples data transmission mode After initialization and synchronization, the serializer accepts parallel data from inputs DIN0 - DIN9. The serializer uses the TCLK input to latch the incoming data. The TCLK_R/F pin selects which edge the serializer uses to strobe incoming data. If either of the SYNC inputs is high for six TCLK cycles, the data at DIN0 -DIN9 is ignored regardless of the clock edge selected and 1026 cycles of SYNC pattern are sent. After determining which clock edge to use, a start and stop bit, appended internally, frames the data bits in the register. The start bit is always high and the stop bit is always low. The start and stop bits function as the embedded clock bits in the serial stream. The serializer transmits serialized data and appended clock bits (10+2 bits) from the serial data output (DO) at 12 times the TCLK frequency. For example, if TCLK is 66 MHz, the serial rate is 66 x 12 = 792 Mbps. Because only 10 bits are input data, the useful data rate is 10 times the TCLK frequency. For instance, if TCLK = 66 MHz, the useful data rate is 66 x 10 = 660 Mbps. The data source, which provides TCLK, must be in the range of 10 MHz to 66 MHz.
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functional description (continued)
The serializer outputs (DO) can drive point-to-point connections or limited multipoint or multidrop backplanes. The outputs transmit data when the enable pin (DEN) is high, PWRDN = high, and SYNC1 and SYNC2 are low. When DEN is driven low, the serializer output pins enter the high-impedance state. Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks to the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low, otherwise ROUT0 - ROUT9 is invalid. The ROUT0-ROUT9 data is strobed out by RCLK. The specific RCLK edge polarity to be used is selected by the RCLK_R/F input. The ROUT0 - ROUT9, LOCK and RCLK outputs can drive a maximum of three CMOS input gates (15-pF load. total for all three) with a 66-MHz clock. power down When no data transfer is required, the power-down mode can be used. The serializer and deserializer use the power-down state, a low-power sleep mode, to reduce power consumption. The deserializer enters power down when you drive PWRDN and REN low. The serializer enters power down when you drive PWRDN low. In power down, the PLL stops and the outputs enter a high-impedance state, which disables load current and reduces supply current to the milliampere range. To exit power down, you must drive the PWRDN pin high. Before valid data exchanges between the serializer and deserializer can resume, you must reinitialize and resynchronize the devices to each other. Initialization of the serializer takes 1026 TCLK cycles. The deserializer initialize and drives LOCK high until lock to the LVDS clock occurs. high-impedance mode The serializer enters the high-impedance mode when the DEN pin is driven low. This puts both driver output pins (DO+ and DO-) into a high-impedance state. When you drive DEN high, the serializer returns to the previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When the REN pin is driven low, the deserializer enters high-impedance mode. Consequently, the receiver output pins (ROUT0 - ROUT9) and RCLK are placed into the high-impedance state. The LOCK output remains active, reflecting the state of the PLL. Deserializer Truth Table
INPUTS PWRDN H H L H REN H H X L ROUT[0:9] Z Active Z Z OUTPUTS LOCK H L Z Active RCLK Z Active Z Z
NOTES: 1. LOCK output reflects the state of the deserializer with regard to the selected data stream. 2. RCLK active indicates the RCLK is running if the deserializer is locked. The timing of RCLK with respect to ROUT is determined by RCLK_R/F. 3. ROUT and RCLK are 3-stated when LOCK is asserted high.
failsafe biasing for the SN65LV1224B The SN65LV1224B has an input threshold sensitivity of 50 mV. This allows for greater differential noise margin in the SN65LV1224B. However, in cases where the receiver input is not being actively driven, the increased sensitivity of the SN65LV1224B can pickup noise as a signal and cause unintentional locking. This may occur when the input cable is disconnected. The SN65LV1224B has an on-chip fail-safe circuit that drives the serial input and LOCK signal high. The response time of the fail-safe circuit depends on interconnect characteristics.
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SN65LV1023A/SN65LV1224B 10 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS621A - SEPTEMBER 2004 - REVISED JANUARY 2005
Terminal Functions serializer
PIN 18, 20, 23, 25 17, 26 19 15, 16 3 -12 21 22 27, 28 24 1, 2 NAME AGND AVCC DEN DGND DIN0 - DIN9 DO - DO + DVCC PWRDN SYNC1, SYNC2 DESCRIPTION Analog circuit ground (PLL and analog circuits) Analog circuit power supply (PLL and analog circuits) LVTTL logic input. Low puts the LVDS serial output into the high-impedance state. High enables serial data output. Digital circuit ground Parallel LVTTL data inputs Inverting LVDS differential output Noninverting LVDS differential output Digital circuit power supply LVTTL logic input. Asserting this pin low turns off the PLL and places the outputs into the high-impedance state, putting the device into a low-power mode. LVTTL logic inputs SYNC1 and SYNC2 are ORed together. When at least one of the two pins is asserted high for 6 cycles of TCLK, the serializer initiates transmission of a minimum 1026 SYNC patterns. If after completion of the transmission of 1026 patterns SYNC continues to be asserted, then the transmission continues until SYNC is driven low and if the time SYNC holds > 6 cycles, another 1026 SYNC pattern tranmission initiates. LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a TCLK rising-edge data strobe. LVTTL-level reference clock input. The SN65LV1023A accepts a 10-MHz to 66-MHz clock. TCLK strobes parallel data into the input latch and provides a reference frequency to the PLL.
13 14
TCLK_R/F TCLK
deserializer
PIN 1, 12, 13 4, 11 14, 20, 22 21, 23 10 7 NAME AGND AVCC DGND DVCC LOCK PWRDN DESCRIPTION Analog circuit ground (PLL and analog circuits) Analog circuit power supply (PLL and analog circuits) Digital circuit ground Digital circuit power supply LVTTL level output. LOCK goes low when the deserializer PLL locks onto the embedded clock edge. LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a high-impedance state, putting the device into a low-power mode. To initiate power down, this pin is held low for a minimum of 16 ns. As long as PWRDN is held low, the device is in the power down state. LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an RCLK rising-edge data strobe. LVTTL level output recovered clock. Use RCLK to strobe ROUTx. LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL frequency. LVTTL logic input. Low places ROUT0-ROUT9 and RCLK in the high-impedance state. Serial data input. Noninverting LVDS differential input Serial data input. Inverting LVDS differential input Parallel LVTTL data outputs
2 9 3 8 5 6 15 -19, 24 -28
RCLK_R/F RCLK REFCLK REN RI+ RI- ROUT0-ROUT9
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absolute maximum ratings (unless otherwise noted)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V LVTTL input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (VCC + 0.3 V) LVTTL output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (VCC + 0.3 V) LVDS receiver input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 3.9 V LVDS driver output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 3.9 V LVDS output short circuit duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ms Electrostatic discharge: HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . up to 6 kV MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . up to 200 V Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature (soldering, 4 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Maximum package power dissipation, TA = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.27 W Package derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 mW/C above 25C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN Supply voltage, VCC} Receiver input voltage range Receiver input common mode range, VCM Supply noise voltage Operating free-air temperature, TA -40 25 V 3 0 ID 2 V 2.4 - NOM 3.3 MAX 3.6 2.4 ID 2 UNIT V V V mVP-P C
100 85
By design, DVCC and AVCC are separated internally and does not matter what the difference is for DVCC-AVCC, as long as both are within 3 V to 3.6 V.
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SN65LV1023A/SN65LV1224B 10 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
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electrical characteristics over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER VIH VIL VCL IIN VIH VIL VCL IIN VOH VOL IOS IOZ VOD VOD VOS VOS IOS IOZ IOX CO VTH VTL IIN CI High-level input voltage Low-level input voltage Input clamp voltage Input current (see Note 5) High-level input voltage Low-level input voltage Input clamp voltage Input current (pull-up and pull-down resistors on inputs) High-level output voltage Low-level output voltage Output short-circuit current High-impedance output current Output differential voltage (DO+)-(DO-) Output differential voltage unbalance Offset voltage Offset voltage unbalance Output short circuit current High-impedance output current Power-off output current Output single-ended capacitance Differential threshold high voltage Differential threshold low voltage Input current Input single-ended capacitance f = 10 MHz f = 66 MHz 20 55 200 f = 10 MHz ICCR Deserializer supply current, worst case CL = 15 pF, See Figure 4 f = 66 MHz 15 80 VIN = 2.4 V, VCC = 3.6 V or 0 V VIN = 0 V, VCC = 3.6 V or 0 V VCM = 1.1 V -50 -10 -10 1 0.05 15 10 0.520% 25 70 500 35 95 mA mA mA A D0 = 0 V, DINx = high, PWRDN and DEN = 2.4 V PWRDN or DEN = 0.8 V, DO = 0 V or VCC VCC = 0 V, DO = 0 V or 3.6 V -10 -20 1.1 1.2 4.8 -10 1 1 ICL = -18 mA VIN = 0 V or 3.6 V IOH = - 5 mA IOL = 5 mA VOUT = 0 V PWRDN or REN = 0.8 V, VOUT = 0 V or VCC RL = 27 , See Figure 19 -200 2.2 GND -15 -10 350 3 0.25 -47 1 450 35 1.3 35 -90 10 25 120% 50 ICL = -18 mA VIN = 0 V or 3.6 V TEST CONDITIONS MIN 2 GND -0.86 -200 2 GND -0.62 100 TYP MAX VCC 0.8 -1.5 200 VCC 0.8 -1.5 200 VCC 0.5 -85 10 UNIT V V V A V V V A V V mA A mV mV V mV mA A A pF mV mV A A pF SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (See Note 4)
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (See Note 6)
SERIALIZER LVDS DC SPECIFICATIONS (Apply to Pins DO+ and DO -)
DESERIALIZER LVDS DC SPECIFICATIONS (Apply to Pins RI+ and RI-)
SERIALIZER SUPPLY CURRENT (Applies to Pins DVCC and AVCC) ICCD Serializer supply current worst case RL = 27 , See Figure 4
ICCXD Serializer supply current PWRDN = 0.8 V DESERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC)
ICCXR Deserializer supply current, power down PWRDN = 0.8 V, REN = 0.8 V 0.36 1 NOTES: 4. Apply to DIN0 -DIN9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, and DEN 5. High IIN values are due to pullup and pulldown resistors on the inputs. 6. Apply to pins PWRDN, RCLK_R/F, REN, and REFCLK = inputs; apply to pins ROUTx, RCLK, and LOCK = outputs
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serializer timing requirements for TCLK over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER tTCP tTCIH tTCIL tt(CLK) tJIT Transmit clock period Transmit clock high time Transmit clock low time TCLK input transition time TCLK input jitter Frequency tolerance See Figure 18 -100 TEST CONDITIONS MIN 15.15 0.4T 0.4T TYP T 0.5T 0.5T 3 MAX 100 0.6T 0.6T 6 150 +100 UNIT ns ns ns ns ps (RMS) ppm
serializer switching characteristics over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER tTLH(L) tLTHL(L) tsu(DI) tsu(DI) td(HZ) td(LZ) td(ZH) td(ZL) tw(SPW) t(PLD) td(S) tDJIT tRJIT LVDS low-to-high transition time LVDS high-to-low transition time DIN0-DIN9 setup to TCLK DIN0-DIN9 hold from TCLK DO high-to-high impedance state delay DO low-to-high impedance state delay DO high-to-high impedance state-tohigh delay DO high-to-high impedance state-to-low delay SYNC pulse duration Serializer PLL lock time Serializer delay 10 MHz Deterministic jitter Random jitter 66 MHz RL = 27 , See Figure 11 RL = 27 , See Figure 12 RL = 27 , CL = 10 pF to GND RL = 2.7 , CL = 10 pF to GND 10 6xtTCP 1026xtTCP tTCP+1 RL = 27 , CL = 10 pF to GND, See Figure 9 TEST CONDITIONS RL = 27 , CL = 10 pF to GND, See Figure 5 RL = 27 , CL = 10 pF to GND, See Figure 8 0.5 4 2.5 2.5 5 6.5 5 5 10 10 ns ns tTCP+2 tTCP+3 230 150 19 ns ps ps (RMS) ns MIN TYP 0.2 0.25 MAX 0.4 0.4 UNIT ns ns ns ns
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SN65LV1023A/SN65LV1224B 10 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
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deserializer timing requirements for REFCLK over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER tRFCP tRFDC tt(RF) REFCLK period REFCLK duty cycle REFCLK transition time Frequency tolerance -100 TEST CONDITIONS MIN 15.15 30% TYP T 50% 3 MAX 100 70% 6 +100 ns ppm UNIT ns
deserializer switching characteristics over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER t(RCP) tTLH(C) Receiver out clock period CMOS/TTL low-to-high transition time CMOS/TTL high-to-low transition time Deserializer delay, See Figure 13 ROUTx data valid before RCLK See Figure 14 t(ROH) t(RDC) td(HZ) ROUTx data valid after RCLK RCLK duty cycle High-to-high impedance state delay Low-to-high impedance state delay High-impedance state to high delay High-impedance state to low delay Deserializer PLL lock time from PWRDN (with SYNCPAT) Deserializer PLL lock time from SYNCPAT High-impedance state to high delay (power up) See Figure 16, Figure 17, and Note 7 10 MHz 66 MHz 10 MHz 66 MHz LOCK TEST CONDITIONS t(RCP) = t(TCP), See Figure 12 PIN/FREQ RCLK MIN 15.15 TYP MAX 100 UNIT ns
1.2 CL = 15 pF, See Figure 6 ROUT0 -ROUT9, LOCK, RCLK 1.1 Room temperature, 3.3 V 10 MHz 66 MHz RCLK 10 MHz RCLK 66 MHz 10 MHz 66 MHz 1.75xt(RCP)+4.2 1.75xt(RCP)+7.4 0.4xt(RCP) 0.4xt(RCP) -0.4xt(RCP) -0.4xt(RCP) 40% 0.5xt(RCP) 0.5xt(RCP) -0.5xt(RCP) -0.5xt(RCP) 50% 6.5
2.5 ns 2.5 1.75xt(RCP)+12.6 1.75xt(RCP)+9.7
tTHL(C) td(D) t(ROS)
ns
ns
60% 8 ns
td(LZ) td(HR) td(ZL) t(DSR1)
4.7 See Figure 15 ROUT0 -ROUT9 5.3 4.7
8
ns
8 8 850 x tRFCP 850 x tRFCP 2 0.303 3
ns ns
s
t(DSR2) td(ZHLK)
ns
The deserializer delay time for all frequencies does not exceed two serial bit times. NOTE 7: t(DSR1) represents the time required for the deserializer to register that a lock has occurred upon powerup or when leaving the powerdown mode. t(DSR2) represents the time required to register that a lock has occurred for the powered up and enabled deserializer when the input (RI) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In order to specify deserializer PLL performance, tDSR1 and tDSR2 are specified with REFCLK active and stable and specific conditions of SYNCPATs.
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deserializer switching characteristics over recommended operating supply and temperature ranges (unless otherwise specified) (continued)
PARAMETER tRNM Deserializer noise margin TEST CONDITIONS See Figure 18 and Note 8 PIN/FREQ 10 MHz 66 MHz MIN TYP 3680 540 ps MAX UNIT
NOTE 8: tRNM represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur.
timing diagrams and test circuits
TCLK
ODD DIN
EVEN DIN
Figure 2. Worst-Case Serializer ICC Test Pattern
SUPPLY CURRENT vs TCLK FREQUENCY
60 66 mA, 48.880 MHz
50 I CC - Supply Current - mA
40 ICC 30
20 10 mA, 14.732 MHz 10
0
0
20
40
60
80
TCLK Frequency - MHz
Figure 3.
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SN65LV1023A/SN65LV1224B 10 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS621A - SEPTEMBER 2004 - REVISED JANUARY 2005
timing diagrams and test circuits (continued)
RCLK
ODD ROUT
EVEN ROUT
Figure 4. Worst-Case Deserializer ICC Test Pattern
10 pF
tTLH(L) DO + RL Vdiff 80% 20% 80% 20%
tTHL(L)
DO - 10 pF
Vdiff = (DO+) - (DO-)
Figure 5. Serializer LVDS Output Load and Transition Times
CMOS/TTL Output tTLH(C) 15 pF 80% 20% 80% 20%
Deserializer
tTHL(C)
Figure 6. Deserializer CMOS/TTL Output Load and Transition Times
tt(CLK) TCLK 90% 10% 90% 10% tt(CLK) 3V 0V
Figure 7. Serializer Input Clock Transition Time
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timing diagrams and test circuits (continued)
tTCP
TCLK
1.5 V
1.5 V
1.5 V
For TCLK_R/F = Low tsu(DI) DIN [9:0] 1.5 V Setup Hold
th(DI)
1.5 V
Figure 8. Serializer Setup/Hold Times
Parasitic Package and Trace Capacitance 3V DEN 0V td(HZ) DO + 13.5 1.1 V DO - DEN 13.5 50% VOL 50% DO VOH 50% 50% 1.1 V td(ZL) 1.1 V td(ZH) 1.5 V 1.5 V
td(LZ)
Figure 9. Serializer High-Impedance State Test Circuit and Timing
PWRDN
2V
0.8 V 1026 Cycles td(HZ) or td(LZ)
TCLK
td(ZH) or td(ZL) tPLD DO 3-State Output Active 3-State
Figure 10. Serializer PLL Lock Time and PWRDN High-Impedance State Delays
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timing diagrams and test circuits (continued)
REN
PWRDN
TCLK
tw(SP) SYNC1 or SYNC2 DO DATA SYNC Pattern
TCLK
SYNC1 or SYNC2 DO
tw(SP) Min. Timing Met
SYNC Pattern
DATA
Figure 11. SYNC Timing Delays
DIN
DIN0 - DIN9 SYMBOL N
DIN0 - DIN9 SYMBOL N+1
td(S) TCLK Timing for TCLK_R/F = High Start D00 - D09 SYMBOL N-1 Bit DO Stop Bit Start Bit D00 - D09 SYMBOL N Stop Bit
Figure 12. Serializer Delay
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timing diagrams and test circuits (continued)
Start Bit RI tDD RCLK Timing for TCLK_R/F = High D00 - D09 SYMBOL N Stop Bit Start Bit D00 - D09 SYMBOL N+1 Stop Bit Start Bit D00 - D09 SYMBOL N+2 Stop Bit
1.2 V 1V
ROUT
ROUT0 - ROUT9 SYMBOL N-1
ROUT0 - ROUT9 SYMBOL N
ROUT0 - ROUT9 SYMBOL N+1
Figure 13. Deserializer Delay
tLow tHigh RCLK RCLK_R/F = Low
tHigh tLow RCLK RCLK_R/F = High tROH tROS ROUT [9:0] 1.5 V
Data Valid Before RCLK Data Valid After RCLK
1.5 V
Figure 14. Deserializer Data Valid Out Times
7 V x (LZ/ZL), Open (HZ/ZH) REN 500 450 Scope VOL td(LZ) VOL + 0.5 V td(HZ) VOH VOH - 0.5 V VOH 1.5 V 1.5 V td(ZL)
50 ROUT[9:0]
VOL
VOL + 0.5 V td(ZH)
VOH - 0.5 V
Figure 15. Deserializer High-Impedance State Test Circuit and Timing
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timing diagrams and test circuits (continued)
PWRDN 2V 0.8 V
REFCLK 1.5 V t(DSR1) DATA RI td(ZHL) LOCK 3-State td(ZH) or td(ZL) ROUT[9:0] 3-State SYNC Symbol or DIN[9:0] td(HZ) or td(LZ) 3-State SYNC Patterns 3-State Not Important
RCLK
3-State RCLK_R/F = Low
3-State
REN
Figure 16. Deserializer PLL Lock Times and PWRDN 3-State Delays
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timing diagrams and test circuits (continued)
3.6 V VCC 3V 0V
PWRDN 0.8 V
REFCLK t(DSR2) RI SYNC Patterns LOCK td(ZH) or td(ZL) ROUT[9:0] 3-State SYNC Symbol or DIN[9:0] 3-State td(HZ) or td(LZ) 3-State
DATA 1.2 V Not Important 1V
RCLK
3-State
3-State
REN
Figure 17. Deserializer PLL Lock Time From SyncPAT
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timing diagrams and test circuits (continued)
1.2 V RI VTH VTL 1V tDJIT tRNM tSW Ideal Sampling Position tSW: Setup and Hold Time (Internal Data Sampling Window) tDJIT: Serializer Output Bit Position Jitter That Results From Jitter on TCLK tRNM: Receiver Noise Margin Time tDJIT tRNM
Figure 18. Receiver LVDS Input Skew Margin
DO +
10 DIN Parallel-to-Serial DO - > TCLK
RL
VOD = (DO+) - (DO-) Differential Output Signal Is Shown as (DO+) - (DO-)
Figure 19. VOD Diagram
device startup procedure
It is recommended that the PWRDNB pin on both the SN65LV1023A and the SN65LV1224B device be held to a logic LOW level until after the power supplies have powered up to at least 3 V as shown in Figure 20.
3.0 V VDD
PWRDNB
Figure 20. Device Startup
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APPLICATION INFORMATION differential traces and termination
The performance of the SN65LV1023A/SN65LV1224B is affected by the characteristics of the transmission medium. Use controlled-impedance media and termination at the receiving end of the transmission line with the media's characteristics impedance. Use balanced cables such as twisted pair or differential traces that are ran close together. A balanced cable picks up noise together and appears to the receiver as common mode. Differential receivers reject common-mode noise. Keep cables or traces matched in length to help reduce skew. Running the differential traces close together helps cancel the external magnetic field, as well as maintain a constant impedance. Avoiding sharp turns and reducing the number of vias also helps.
topologies
There are several topologies that the serializers can operate. Three common examples are shown below. Figure 21 shows an example of a single-terminated point-to-point connection. Here a single termination resistor is located at the deserializer end. The resistor value should match that of the characteristic impedance of the cable or PC board traces. The total load seen by the serializer is 100 . Double termination can be used and typically reduces reflections compared with single termination. However, it also reduces the differential output voltage swing. AC-coupling is only recommended if the parallel TX data stream is encoded to achieve a dc-balanced data stream. Otherwise the ac-capicitors can induce common mode voltage drift due to the dc-unbalanced data stream.
Serialized Data Parallel Data In 100 Parallel Data Out
Figure 21. Single-Terminated Point-to-Point Connection Figure 22 shows an example of a multidrop configuration. Here there is one transmitter broadcasting data to multiple receivers. A 50-k resistor at the far end terminates the bus.
ASIC
ASIC
ASIC
ASIC
50
Figure 22. Multidrop Configuration
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SN65LV1023A/SN65LV1224B 10 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
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Figure 23 shows an example of multiple serializers and deserializers on the same differential bus, such as in a backplane. This is a multipoint configuration. In this situation, the characteristic impedance of the bus can be significantly less due to loading. Termination resistors that match the loaded characteristic impedance are required at each end of the bus. The total load seen by the serializer in this example is 27 .
ASIC
ASIC
ASIC
ASIC
54
54
Figure 23. Multiple Serializers and Deserializers on the Same Differential Bus
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2005
PACKAGING INFORMATION
Orderable Device SN65LV1023ADB SN65LV1023ADBR SN65LV1224BDB SN65LV1224BDBR
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SSOP SSOP SSOP SSOP
Package Drawing DB DB DB DB
Pins Package Eco Plan (2) Qty 28 28 28 28 50 2000 50 2000 Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-2-260C-1YEAR/ Level-1-220C-UNLIM Level-2-260C-1YEAR/ Level-1-220C-UNLIM Level-2-260C-1YEAR/ Level-1-220C-UNLIM Level-2-260C-1YEAR/ Level-1-220C-UNLIM
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 0,95 0,55
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 /E 12/01
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
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